1. Field of the Invention
This invention relates to an FIFO (first-in first-out) memory device and an application device thereof, and more particularly to an FIFO memory device used for a distribution circuit, synthesizing circuit, etc., of image data for parallel processing to speed up graphics processing at a three-dimensional graphics display or the like.
2. Description of the Related Art
FIG. 1 shows a conventional FIFO memory device where fixed-length data is input one word at a time and one data item consisting of words is output in parallel at the same time. Assume that for example, the FIFO memory device comprises four normal FIFO memory cells 101-104, each of which one word (in this case, eight bits) is input to and output from. The entire FIFO memory device is designed to input data one word at a time and output four words (8.times.4 bits) in parallel.
To execute input operation to such an FIFO memory device, a host central processing unit 105 needs to recognize that four FIFO memory cells 101-104 exist, and address the four FIFO memory cells 101-104 in sequence to write data into the four cells 101-104 in sequence one word at a time.
For such a conventional FIFO memory device, the host central processing unit 105 must recognize the FIFO memory cells separately for addressing, thus perform complicated write control. On the other hand, to speed up graphics processing at three-dimensional graphics displays, etc., demand is placed for relieving the host central processing unit 105 of its work load as much as possible.
A memory array consisting of memory cells arrayed like a matrix is used for a conventional FIFO memory device where variable-length data is input one word at a time and one data item consisting of words is output in parallel at the same time; input data is written, one word at a time, starting at the beginning of each row and on the other hand, the words in all columns within one row are read out at the same time.
To read out data in such a manner, two data items are prevented from being written into one row of the memory array. That is, if data write terminates at an intermediate point of one row of the memory array, dummy data is written into the remaining columns of the row.
FIG. 2 illustrates the dummy data write.
Assume that input data 106 has, for example, the entire length of seven words, namely, consists of 1-word command data and 6-word parameter data, as shown in FIG. 2(a), and that a memory array 107 consists of three rows.times.six columns of memory cells, as shown in (b) and (c).
In FIG. 2, to write the input data 106 into the memory array 107 one word at a time, parameter data 6 of the seventh word of the input data 106 is written into a memory cell on the next row as shown in (b). If the next input data is written into the memory cell contiguous to the memory cell where the parameter data 6 is written, output data contains the two separate data items when all columns of the row are read out at a time (see arrows in the figure).
To avoid this problem, dummy data is written into the remaining columns and the next data is written into the next row, as shown in (c).
However, address control to accomplish data write in this manner becomes complicated and consumes considerable time; this is an obstacle to speeding up graphics processing at a three-dimensional graphics display, etc.
For data read out for each row from the memory array 107, the number of bytes of one data item is unknown. Thus, when variable-length data read out is disassembled into words, dummy data other than the original words making up data is also handled as words.
To speed up graphics processing, some three-dimensional graphics display is provided with three-dimensional frame memories (3D-FMs) 110-113, as shown in FIG. 3; partial image data pieces generated by image processing blocks (not shown), which are different from each other, are written into the 3D-FMs and then the image data pieces written into the 3D-FMs 110-113 are synthesized by image synthesizing blocks 114-116.
Each of the image synthesizing blocks 114-116 synthesizes the image data written into the 3D-FM in its own unit with the image data transferred from the unit at the preceding stage (in FIG. 3, the unit to the left of its own unit). A display block 117 displays the final image data synthesized. Unit 0 generates basic image data and units 1 to n are added in sequence according to the necessity of high speed processing and the complexity of images.
The image synthesizing blocks 114-116 of the three-dimensional graphics display must synchronize with each other when synthesizing image data from the preceding unit with image data from the 3D-FM of its own unit. Thus, each of the image synthesizing blocks 114-116 is provided with a register for giving a given amount of delay to the input timing of the image data from the preceding unit to absorb synchronization shift caused by clock shift or a delay at image data transfer in each unit.
However, the conventional method contains a disadvantage in that synchronization shift caused by a temperature change or parts variation cannot precisely be adjusted because the synchronization adjustment amount (delay amount in each register) is constant. Since the three-dimensional graphics display is made up of a large number of units which are connected, as shown in FIG. 3, it is necessary to set the synchronization amount for each connection and also to make the registers in the units separately.